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author
Pasquale Davide Schiavone
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Update muldiv module
1 parent b2a0944 commit fe8f4fd

10 files changed

Lines changed: 489 additions & 196 deletions

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‎alu.sv‎

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -34,10 +34,10 @@ module zeroriscy_alu
3434
input logic [31:0] operand_a_i,
3535
input logic [31:0] operand_b_i,
3636

37-
input logic [32:0] mult_operand_a_i,
38-
input logic [32:0] mult_operand_b_i,
37+
input logic [32:0] multdiv_operand_a_i,
38+
input logic [32:0] multdiv_operand_b_i,
3939

40-
input logic mult_en_i,
40+
input logic multdiv_en_i,
4141

4242
output logic [31:0] adder_result_o,
4343
output logic [33:0] adder_result_ext_o,
@@ -95,14 +95,14 @@ module zeroriscy_alu
9595
end
9696

9797
// prepare operand a
98-
assign adder_in_a = mult_en_i ? mult_operand_a_i : {operand_a_i,1'b1};
98+
assign adder_in_a = multdiv_en_i ? multdiv_operand_a_i : {operand_a_i,1'b1};
9999

100100
// prepare operand b
101-
assign adder_in_b = {operand_b_i,1'b0};
102-
assign operand_b_neg = mult_en_i ? mult_operand_b_i : adder_in_b ^ {33{adder_op_b_negate}};
101+
assign operand_b_neg = {operand_b_i,1'b0} ^ {33{adder_op_b_negate}};
102+
assign adder_in_b = multdiv_en_i ? multdiv_operand_b_i : operand_b_neg ;
103103

104104
// actual adder
105-
assign adder_result_ext_o = $unsigned(adder_in_a) + $unsigned(operand_b_neg);
105+
assign adder_result_ext_o = $unsigned(adder_in_a) + $unsigned(adder_in_b);
106106

107107
assign adder_result = adder_result_ext_o[32:1];
108108

‎decoder.sv‎

Lines changed: 40 additions & 40 deletions
Original file line numberDiff line numberDiff line change
@@ -56,9 +56,9 @@ module zeroriscy_decoder
5656
output logic [3:0] imm_b_mux_sel_o, // immediate selection for operand b
5757

5858
// MUL related control signals
59-
output logic mult_int_en_o, // perform integer multiplication
60-
output logic [1:0] mult_operator_o,
61-
output logic [1:0] mult_signed_mode_o,
59+
output logic multdiv_int_en_o, // perform integer multiplication
60+
output logic [1:0] multdiv_operator_o,
61+
output logic [1:0] multdiv_signed_mode_o,
6262
// register file related signals
6363
output logic regfile_we_o, // write enable for regfile
6464

@@ -88,7 +88,7 @@ module zeroriscy_decoder
8888
logic mret_insn;
8989
logic pipe_flush;
9090

91-
logic mult_int_en;
91+
logic multdiv_int_en;
9292
logic branch_in_id;
9393
logic jump_in_id;
9494

@@ -115,9 +115,9 @@ module zeroriscy_decoder
115115
imm_a_mux_sel_o = IMMA_ZERO;
116116
imm_b_mux_sel_o = IMMB_I;
117117

118-
mult_int_en = 1'b0;
119-
mult_operator_o = MUL_L;
120-
mult_signed_mode_o = 2'b00;
118+
multdiv_int_en = 1'b0;
119+
multdiv_operator_o = MD_OP_MULL;
120+
multdiv_signed_mode_o = 2'b00;
121121

122122
regfile_we = 1'b0;
123123

@@ -399,52 +399,52 @@ module zeroriscy_decoder
399399

400400
// supported RV32M instructions
401401
{6'b00_0001, 3'b000}: begin // mul
402-
alu_operator_o = ALU_ADD;
403-
mult_operator_o = MUL_L;
404-
mult_int_en = 1'b1;
405-
mult_signed_mode_o = 2'b00;
402+
alu_operator_o = ALU_ADD;
403+
multdiv_operator_o = MD_OP_MULL;
404+
multdiv_int_en = 1'b1;
405+
multdiv_signed_mode_o = 2'b00;
406406
end
407407
{6'b00_0001, 3'b001}: begin // mulh
408-
alu_operator_o = ALU_ADD;
409-
mult_operator_o = MUL_H;
410-
mult_int_en = 1'b1;
411-
mult_signed_mode_o = 2'b11;
408+
alu_operator_o = ALU_ADD;
409+
multdiv_operator_o = MD_OP_MULH;
410+
multdiv_int_en = 1'b1;
411+
multdiv_signed_mode_o = 2'b11;
412412
end
413413
{6'b00_0001, 3'b010}: begin // mulhsu
414-
alu_operator_o = ALU_ADD;
415-
mult_operator_o = MUL_H;
416-
mult_int_en = 1'b1;
417-
mult_signed_mode_o = 2'b01;
414+
alu_operator_o = ALU_ADD;
415+
multdiv_operator_o = MD_OP_MULH;
416+
multdiv_int_en = 1'b1;
417+
multdiv_signed_mode_o = 2'b01;
418418
end
419419
{6'b00_0001, 3'b011}: begin // mulhu
420-
alu_operator_o = ALU_ADD;
421-
mult_operator_o = MUL_H;
422-
mult_int_en = 1'b1;
423-
mult_signed_mode_o = 2'b00;
420+
alu_operator_o = ALU_ADD;
421+
multdiv_operator_o = MD_OP_MULH;
422+
multdiv_int_en = 1'b1;
423+
multdiv_signed_mode_o = 2'b00;
424424
end
425425
{6'b00_0001, 3'b100}: begin // div
426-
alu_operator_o = ALU_ADD;
427-
mult_operator_o = DIV;
428-
mult_int_en = 1'b1;
429-
mult_signed_mode_o = 2'b11;
426+
alu_operator_o = ALU_ADD;
427+
multdiv_operator_o = MD_OP_DIV;
428+
multdiv_int_en = 1'b1;
429+
multdiv_signed_mode_o = 2'b11;
430430
end
431431
{6'b00_0001, 3'b101}: begin // divu
432-
alu_operator_o = ALU_ADD;
433-
mult_operator_o = DIV;
434-
mult_int_en = 1'b1;
435-
mult_signed_mode_o = 2'b00;
432+
alu_operator_o = ALU_ADD;
433+
multdiv_operator_o = MD_OP_DIV;
434+
multdiv_int_en = 1'b1;
435+
multdiv_signed_mode_o = 2'b00;
436436
end
437437
{6'b00_0001, 3'b110}: begin // rem
438-
alu_operator_o = ALU_ADD;
439-
mult_operator_o = REM;
440-
mult_int_en = 1'b1;
441-
mult_signed_mode_o = 2'b11;
438+
alu_operator_o = ALU_ADD;
439+
multdiv_operator_o = MD_OP_REM;
440+
multdiv_int_en = 1'b1;
441+
multdiv_signed_mode_o = 2'b11;
442442
end
443443
{6'b00_0001, 3'b111}: begin // remu
444-
alu_operator_o = ALU_ADD;
445-
mult_operator_o = REM;
446-
mult_int_en = 1'b1;
447-
mult_signed_mode_o = 2'b00;
444+
alu_operator_o = ALU_ADD;
445+
multdiv_operator_o = MD_OP_REM;
446+
multdiv_int_en = 1'b1;
447+
multdiv_signed_mode_o = 2'b00;
448448
end
449449
default: begin
450450
illegal_insn_o = 1'b1;
@@ -559,7 +559,7 @@ module zeroriscy_decoder
559559

560560
// deassert we signals (in case of stalls)
561561
assign regfile_we_o = (deassert_we_i) ? 1'b0 : regfile_we;
562-
assign mult_int_en_o = (deassert_we_i) ? 1'b0 : mult_int_en;
562+
assign multdiv_int_en_o = (deassert_we_i) ? 1'b0 : multdiv_int_en;
563563
assign data_req_o = (deassert_we_i) ? 1'b0 : data_req;
564564
assign csr_op_o = (deassert_we_i) ? CSR_OP_NONE : csr_op;
565565
assign jump_in_id_o = (deassert_we_i) ? 1'b0 : jump_in_id;

‎ex_stage.sv‎

Lines changed: 50 additions & 50 deletions
Original file line numberDiff line numberDiff line change
@@ -40,15 +40,15 @@ module zeroriscy_ex_block
4040

4141
// ALU signals from ID stage
4242
input logic [ALU_OP_WIDTH-1:0] alu_operator_i,
43-
input logic [1:0] mult_operator_i,
44-
input logic mult_en_i,
43+
input logic [1:0] multdiv_operator_i,
44+
input logic multdiv_en_i,
4545

4646
input logic [31:0] alu_operand_a_i,
4747
input logic [31:0] alu_operand_b_i,
4848

49-
input logic [1:0] mult_signed_mode_i,
50-
input logic [31:0] mult_operand_a_i,
51-
input logic [31:0] mult_operand_b_i,
49+
input logic [1:0] multdiv_signed_mode_i,
50+
input logic [31:0] multdiv_operand_a_i,
51+
input logic [31:0] multdiv_operand_b_i,
5252

5353
output logic [31:0] alu_adder_result_ex_o,
5454
output logic [31:0] regfile_wdata_ex_o,
@@ -66,18 +66,18 @@ module zeroriscy_ex_block
6666

6767
localparam MULT_TYPE = 0; //0 is SLOW
6868

69-
logic [31:0] alu_result, mult_result;
69+
logic [31:0] alu_result, multdiv_result;
7070

71-
logic [32:0] mult_alu_operand_a_sel, mult_alu_operand_b_sel, mult_alu_operand_a, mult_alu_operand_b;
71+
logic [32:0] multdiv_alu_operand_a_sel, multdiv_alu_operand_b_sel, multdiv_alu_operand_a, multdiv_alu_operand_b;
7272
logic [33:0] alu_adder_result_ext;
7373
logic alu_cmp_result, alu_is_equal_result;
74-
logic mult_ready, mult_en_sel;
74+
logic multdiv_ready, multdiv_en_sel;
7575

76-
assign mult_en_sel = MULT_TYPE == 0 ? mult_en_i : 1'b0;
77-
assign mult_alu_operand_a_sel = MULT_TYPE == 0 ? mult_alu_operand_a : alu_operand_a_i;
78-
assign mult_alu_operand_b_sel = MULT_TYPE == 0 ? mult_alu_operand_b : alu_operand_b_i;
76+
assign multdiv_en_sel = MULT_TYPE == 0 ? multdiv_en_i : 1'b0;
77+
assign multdiv_alu_operand_a_sel = MULT_TYPE == 0 ? multdiv_alu_operand_a : alu_operand_a_i;
78+
assign multdiv_alu_operand_b_sel = MULT_TYPE == 0 ? multdiv_alu_operand_b : alu_operand_b_i;
7979

80-
assign regfile_wdata_ex_o = mult_en_i ? mult_result : alu_result;
80+
assign regfile_wdata_ex_o = multdiv_en_i ? multdiv_result : alu_result;
8181

8282
// branch handling
8383
assign branch_decision_o = alu_cmp_result;
@@ -94,57 +94,57 @@ module zeroriscy_ex_block
9494

9595
zeroriscy_alu alu_i
9696
(
97-
.operator_i ( alu_operator_i ),
98-
.operand_a_i ( alu_operand_a_i ),
99-
.operand_b_i ( alu_operand_b_i ),
100-
.mult_operand_a_i ( mult_alu_operand_a_sel ),
101-
.mult_operand_b_i ( mult_alu_operand_b_sel ),
102-
.mult_en_i ( mult_en_sel ),
103-
.adder_result_o ( alu_adder_result_ex_o ),
104-
.adder_result_ext_o ( alu_adder_result_ext ),
105-
.result_o ( alu_result ),
106-
.comparison_result_o ( alu_cmp_result ),
107-
.is_equal_result_o ( alu_is_equal_result )
97+
.operator_i ( alu_operator_i ),
98+
.operand_a_i ( alu_operand_a_i ),
99+
.operand_b_i ( alu_operand_b_i ),
100+
.multdiv_operand_a_i ( multdiv_alu_operand_a_sel ),
101+
.multdiv_operand_b_i ( multdiv_alu_operand_b_sel ),
102+
.multdiv_en_i ( multdiv_en_sel ),
103+
.adder_result_o ( alu_adder_result_ex_o ),
104+
.adder_result_ext_o ( alu_adder_result_ext ),
105+
.result_o ( alu_result ),
106+
.comparison_result_o ( alu_cmp_result ),
107+
.is_equal_result_o ( alu_is_equal_result )
108108
);
109109

110-
if (MULT_TYPE == 0) begin : mult_slow
111-
zeroriscy_mult_slow mult_i
110+
if (MULT_TYPE == 0) begin : multdiv_slow
111+
zeroriscy_multdiv_slow multdiv_i
112112
(
113-
.clk ( clk ),
114-
.rst_n ( rst_n ),
115-
.mult_en_i ( mult_en_i ),
116-
.operator_i ( mult_operator_i ),
117-
.signed_mode_i ( mult_signed_mode_i ),
118-
.op_a_i ( mult_operand_a_i ),
119-
.op_b_i ( mult_operand_b_i ),
120-
.alu_adder_ext_i ( alu_adder_result_ext ),
121-
.alu_adder_i ( alu_adder_result_ex_o ),
122-
.equal_to_zero ( alu_is_equal_result ),
123-
.ready_o ( mult_ready ),
124-
.alu_operand_a_o ( mult_alu_operand_a ),
125-
.alu_operand_b_o ( mult_alu_operand_b ),
126-
.mult_result_o ( mult_result )
113+
.clk ( clk ),
114+
.rst_n ( rst_n ),
115+
.multdiv_en_i ( multdiv_en_i ),
116+
.operator_i ( multdiv_operator_i ),
117+
.signed_mode_i ( multdiv_signed_mode_i ),
118+
.op_a_i ( multdiv_operand_a_i ),
119+
.op_b_i ( multdiv_operand_b_i ),
120+
.alu_adder_ext_i ( alu_adder_result_ext ),
121+
.alu_adder_i ( alu_adder_result_ex_o ),
122+
.equal_to_zero ( alu_is_equal_result ),
123+
.ready_o ( multdiv_ready ),
124+
.alu_operand_a_o ( multdiv_alu_operand_a ),
125+
.alu_operand_b_o ( multdiv_alu_operand_b ),
126+
.multdiv_result_o ( multdiv_result )
127127
);
128128
end else begin: mult_fast
129129
zeroriscy_mult_fast mult_i
130130
(
131-
.clk ( clk ),
132-
.rst_n ( rst_n ),
133-
.mult_en_i ( mult_en_i ),
134-
.operator_i ( mult_operator_i ),
135-
.signed_mode_i ( mult_signed_mode_i ),
136-
.op_a_i ( mult_operand_a_i ),
137-
.op_b_i ( mult_operand_b_i ),
138-
.ready_o ( mult_ready ),
139-
.mult_result_o ( mult_result )
131+
.clk ( clk ),
132+
.rst_n ( rst_n ),
133+
.multdiv_en_i ( multdiv_en_i ),
134+
.operator_i ( multdiv_operator_i ),
135+
.signed_mode_i ( multdiv_signed_mode_i ),
136+
.op_a_i ( multdiv_operand_a_i ),
137+
.op_b_i ( multdiv_operand_b_i ),
138+
.ready_o ( multdiv_ready ),
139+
.multdiv_result_o ( multdiv_result )
140140
);
141141
end
142142

143143
always_comb
144144
begin
145145
unique case (1'b1)
146-
mult_en_i:
147-
ex_ready_o = mult_ready;
146+
multdiv_en_i:
147+
ex_ready_o = multdiv_ready;
148148
lsu_en_i:
149149
ex_ready_o = lsu_ready_ex_i;
150150
default:

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