Discussion Type

General

Discussion Content

Hello CircuitVerse mentors and contributors,

I’m preparing my GSoC 2026 proposal for Project 3: FSM to Circuit Synthesizer and would really appreciate early feedback on scope and technical direction.

Current draft materials

One-page design: [06-One-Page-Design.md]
Timeline and milestones: [02-Timeline-and-Milestones.md
Proposed MVP boundaries

Structured/tabular FSM input only (no advanced graphical editor initially)
Deterministic validation + binary state encoding
Boolean equation generation for next-state/output logic
Circuit mapping to editable CircuitVerse-compatible output
Recent contributions

[https://github.com/CircuitVerse/CircuitVerse/pull/7110]
[https://github.com/CircuitVerse/CircuitVerse/pull/7111
Questions for mentor alignment

Is this MVP scope realistic for a 175-hour project?
For lower implementation risk, should I sequence Moore-first and then Mealy, or build both in parallel?
Which existing simulator/data-flow interfaces should I integrate with first for best maintainability and reviewability?
I’m also building a small POC to validate conversion flow and will share it in this thread shortly.

Thank you for your guidance.
06-One-Page-Design.md
02-Timeline-and-Milestones.md