From c1eae358015362e8f0854472b440bce019ee9351 Mon Sep 17 00:00:00 2001
From: Stefan Wallentowitz <stefan.wallentowitz@hm.edu>
Date: Fri, 1 Jul 2022 17:46:10 +0200
Subject: [PATCH] Minor fixes

---
 riscvmodel/golden.py | 6 +++---
 riscvmodel/insn.py   | 2 +-
 riscvmodel/isa.py    | 4 ++--
 riscvmodel/random.py | 1 -
 riscvmodel/types.py  | 2 +-
 5 files changed, 7 insertions(+), 8 deletions(-)

diff --git a/riscvmodel/golden.py b/riscvmodel/golden.py
index a5f42f3..11affe7 100644
--- a/riscvmodel/golden.py
+++ b/riscvmodel/golden.py
@@ -3,7 +3,7 @@
 
 from .variant import Variant
 from .model import Model, Memory
-from .isa import InstructionNOP
+from .insn import InstructionNOP
 from .program import Program
 from .types import RVFISignals, TraceIntegerRegister, Register
 from .code import decode
@@ -66,8 +66,8 @@ def commit(self, trace, *, insn = None):
         # Execute the expected instruction and verify the state is the same
         exp_trace = self.model.issue(exp)
         if not self.model.check(trace):
-            raise GoldenException("Unexpected state change: {}, expected: {}".format(",".join([str(t) for t in trace]),
-                                                                                     ",".join([str(t) for t in exp_trace])))
+            raise GoldenException("Unexpected state change: {}, expected: {}, insn: {}".format(",".join([str(t) for t in trace]),
+                                                                                          ",".join([str(t) for t in exp_trace]), insn))
 
     def reset(self, *, pc: int = 0):
         self.model.reset(pc=pc)
diff --git a/riscvmodel/insn.py b/riscvmodel/insn.py
index d1b00b8..f7e702b 100644
--- a/riscvmodel/insn.py
+++ b/riscvmodel/insn.py
@@ -203,7 +203,7 @@ def execute(self, model: Model):
 @isa("srai", RV32I, opcode=0b0010011, funct3=0b101, funct7=0b0100000)
 class InstructionSRAI(InstructionISType):
     def execute(self, model: Model):
-        model.state.intreg[self.rd] = model.state.intreg[self.rs1] >> self.shamt
+        model.state.intreg[self.rd] = model.state.intreg[self.rs1] >> int(self.shamt)
 
 
 @isa("add", RV32I, opcode=0b0110011, funct3=0b000, funct7=0b0000000)
diff --git a/riscvmodel/isa.py b/riscvmodel/isa.py
index 868abdd..4e55698 100644
--- a/riscvmodel/isa.py
+++ b/riscvmodel/isa.py
@@ -202,10 +202,10 @@ def __setattr__(self, key, value):
     def __eq__(self, other):
         for field in self.get_fields():
             if field.static:
-                if getattr(self, field) != getattr(other, field):
+                if getattr(self, f"field_{field.name}") != getattr(other, f"field_{field.name}"):
                     return False
             else:
-                if getattr(self, field[6:]) != getattr(other, field[6:]):
+                if getattr(self, field.name) != getattr(other, field.name):
                     return False
         return True
 
diff --git a/riscvmodel/random.py b/riscvmodel/random.py
index e169f16..4f3f40c 100644
--- a/riscvmodel/random.py
+++ b/riscvmodel/random.py
@@ -8,7 +8,6 @@
 from .isa import get_insns
 from .variant import Variant, RV32I
 from .code import read_from_binary
-from .model import Model
 from . import __version__
 
 
diff --git a/riscvmodel/types.py b/riscvmodel/types.py
index b59164a..7034993 100644
--- a/riscvmodel/types.py
+++ b/riscvmodel/types.py
@@ -226,7 +226,7 @@ def __lshift__(self, other):
 
     def __rshift__(self, other):
         new = Register(self.bits)
-        value = (self.value + 2**self.bits) if self.value < 0 else self.value
+        value = self.value
         if isinstance(other, int):
             new.set(value >> other)
         elif isinstance(other, (Register, Immediate)):